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參數(shù)資料
| 型號： | EP9301-IQ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM920T MCU 166MHZ 208-LQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | EP9 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 166MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，SPI，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，LED，MaverickKey，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 19 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 208-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 598-1249 |
2
ER636E2
B
Ethernet
Description 1
The Ethernet controller does not correctly receive frames that have a size of 64 bytes.
Workaround
In order to receive frames of 64 bytes, enable the RCRCA bit in RxCTL. This will prevent the Ethernet
controller from discarding the 64-byte-long frames.
Description 2
When there is inadequate AHB bus bandwidth for data to be transferred from the Ethernet controller FIFO
to the receive descriptor, the Ethernet FIFO will overflow and cause the Ethernet controller to fail to receive
any more packets.
This problem will also occur if the processor is too busy to service incoming packets in a timely manner. By
the time that new receive descriptors are available, the data in the FIFO will contain frames that are
corrupted.
It is the job of the system designer to ensure that there is adequate bandwidth for the applications being run.
Workaround
This is a rare occurrence, however at a system level it is important to reserve adequate bandwidth for the
Ethernet controller. This can be accomplished by some of the following:
- Reducing the bandwidth use of other bus masters in the system.
- Lowering Ethernet rate to half duplex or 10Mbit if higher bandwidth is not required.
- Insuring that the Ethernet controller receive descriptor processing is given a high enough priority to
ensure that the controller never runs out of receive descriptors.
HDLC
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To insure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP9301-IQZ | 功能描述:微處理器 - MPU IC Entry-Level ARM9 SOC Processor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| EP9302 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:High-speed ARM9 System-on-chip Processor with MaverickCrunch |
| EP9302A-Z | 制造商:Cirrus Logic 功能描述:- Bulk |
| EP9302-CQ | 制造商:Cirrus Logic 功能描述: |
| EP9302-CQ/E1 | 制造商:Cirrus Logic 功能描述: |
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