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參數(shù)資料
| 型號： | EP9307-CR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM920T MCU 200MHZ 272-TFBGA |
| 標準包裝： | 119 |
| 系列： | EP9 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，SPI，UART/USART，USB |
| 外圍設備： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 14 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 272-TFBGA |
| 包裝： | 托盤 |
| 配用： | 598-1133-ND - KIT DEVELOPMENT EP9307 ARM9 |
| 其它名稱： | 598-1254 |
ER667E2B
5
USB
Description 1
USB clock divider logic operates at a maximum rate of 288MHz under worst case conditions.
Workaround
When using USB, make sure the clock frequency supplied to the USB clock divider does not exceed
288MHz. The clock supplied to the USB clock divider is sourced by PLL2. The USB clock divider is
controlled by the USBDIV setting in the CLKSET2 register. For example, configure PLL2 to output 192MHz
and USBDIV to divide by four. Ensure that the new PLL2 setting does not adversely affect any other block
using PLL2 as its clock source.
NOTE: PLL2 is completely functional. This is only an issue with the USB clock divider logic.
ExtensionID Register
Description
The PartID field in register 0x8083_2714, ExtensionID, is not programmed.
Workaround
None, this register has been de-featured from the chip.
Reset
Description
The processor may boot into an invalid state upon initial power up of the device. When this condition occurs,
the processor will not complete its boot sequence and requires an additional power on reset (POR) to be
applied.
Workaround
Implement the recommended external reset circuit described in AN258, “EP93xx Power-up and Reset
Lockup Workaround,” which can be found at http://www.cirrus.com/en/pubs/appNote/AN258REV2.pdf.
Boot Configuration
Description
The processor may incorrectly latch the state of the CSn[7:6, 3:0] lines. The only problematic effect of this
condition is that the device may attempt to perform a 32-bit boot when it is actually configured for 16-bit boot
mode.
Workaround
Implement the recommendations described in AN273, item 7, “EP93xx Silicon Rev E Design Guidelines,”
which can be found at http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP9307-CR/E1 | 制造商:Cirrus Logic 功能描述: |
| EP9307-CRR | 功能描述:微處理器 - MPU IC Universal Platfrm ARM9 SOC Prcessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| EP9307CRZ | 制造商:Cirrus Logic 功能描述: |
| EP9307-CRZ | 功能描述:微處理器 - MPU IC Universl Pltform ARM9 SOC Prcessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| EP9307-CRZR | 功能描述:微處理器 - MPU IC Universal Platfrm ARM9 SOC Prcessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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