Raster EP9312 User's Guide Update As designed, horizontal clock and data are not aligned. Where horizontal clock gating is required," />
參數(shù)資料
型號(hào): EP9307-CRZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC ARM920T 200MHZ PROC 272 TFBGA
標(biāo)準(zhǔn)包裝: 500
系列: EP9
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 200MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,鍵盤/觸摸屏,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-LFBGA
其它名稱: Q5809834A
4
ER667E2B
Raster
EP9312 User's Guide Update
As designed, horizontal clock and data are not aligned. Where horizontal clock gating is required, set
HACTIVESTRTSTOP equal to HCLKSTRTSTOP+5.
Description 1
If the raster engine is using single scan mode, two and two thirds per pixel mode (3 bits per pixel over an 8-
bit bus) works correctly. If the raster engine is programmed to use two and two thirds pixels per clock shift
mode with dual scan enabled, it will not generate valid timings for dual scan displays.
Workaround
There is no known workaround at this time.
Description 2
YCrCb formatted video will not produce the valid synchronization signals in 656 video mode.
Workaround
Design the system with an NTSC/PAL DAC that accepts RGB input signals.
RTC
Description
The internal RTC oscillator is susceptible to noise which can lead to extra clocks on the internal 32.768-kHz
signal.
Workaround
Please refer to application note AN265, “EP93xx RTC Oscillator Circuit”, which can be found at
No fix of this bug is planned for future silicon revisions.
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