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參數(shù)資料
| 型號： | EPC1213PI8 |
| 廠商： | Altera |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 212KBIT 8-DIP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 100 |
| 系列： | EPC |
| 可編程類型： | OTP |
| 存儲容量： | 212kb |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 配用： | PLMJ1213-ND - PROGRAMMER ADAPTER 20 PIN J-LEAD |
| 其它名稱： | 544-1370-5 EPC1213PI8-ND |
Functional Description
Page 5
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Figure 1 shows the configuration device block diagram.
Stratix II
EP2S15
5,000,000
—
3
EP2S30
10,100,000
—
7
EP2S60
17,100,000
—
———11
EP2S90
27,500,000
—
———17
EP2S130
39,600,000
—
———24
EP2S180
52,400,000
—
———31
Notes to Table 2:
(1) Raw Binary File (.rbf) were used to determine these sizes.
(2) This number is calculated with the Cyclone series compression feature enabled.
(3) EP1S10 ES devices requires four EPC2 devices.
Table 2. Supported Configuration Devices (Part 4 of 4)
Device Family
Device
Data Size (Bits)
(1)
EPC1064 or
EPC1064V
EPC1213
EPC1441
EPC1
EPC2
Figure 1. Configuration Device Block Diagram
Notes to Figure 1:
(1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading.
(2) The OE pin is a bidirectional open-drain pin.
DCLK
nCS
OE
Decode
Logic
Address
DATA
Shift
Register
EPROM
Array
nCS
Decode
Logic
Address
Oscillator
Control
EPROM
Array
Shift
Register
DATA
DCLK
nCASC
(1)
FPGA (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441
FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V
Address
Counter
CLK
ENA
nRESET
Error
Detection
Circuitry
OE
Address
Counter
CLK
ENA
nRESET
(2)
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