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參數(shù)資料
| 型號： | EPC1441TC32N |
| 廠商： | Altera |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 440KBIT 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | EPC |
| 可編程類型： | OTP |
| 存儲容量： | 440kb |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 544-1649 |
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Page 22
Pin Information
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
nCS
49
10
Input
Chip select input (active low). The nCS pin connects to the
CONF
_DONE pin of the FPGA.
A low input allows DCLK to increment the address counter
and enables DATA to drive out. If the EPC1 or EPC2 device
is reset (OE pulled low) while nCS is low, the device
initializes as the master device in a configuration chain. If
the EPC1 or EPC2 device is reset (OE pulled low) while nCS
is high, the device initializes as a slave device in the chain.
The nCS pin has an internal programmable 1-k
resistor
in EPC2 devices. If internal pull-up resistors are used, do
not use external pull-up resistors on these pins. You can
disable the internal pull-up resistors through the Disable
nCS and OE pull-ups on configuration device option.
nCASC
612
15
Output
Cascade select output (active low).
This output goes low when the address counter has
reached its maximum value. When the address counter has
reached its maximum value, the configuration device has
sent all its configuration data to the FPGA. In a chain of
EPC1 or EPC2 devices, the nCASC pin of one device is
connected to the nCS pin of the next device, which permits
DCLK
to clock data from the next EPC1 or EPC2 device in
the chain. For single EPC1 or EPC2 device and the last
device in the chain, nCASC is left floating.
This pin is only available in EPC1 and EPC2 devices, which
support data cascading.
nINIT
_CONF
N/A
13
16
Open-Drain
Output
Allows the INIT_CONF JTAG instruction to initiate
configuration. The nINIT_CONF pin connects to the
nCONFIG
pin of the FPGA.
If multiple EPC2 devices are used to configure an FPGA,
the nINIT_CONF of the first EPC2 device pin is tied to the
FPGA’s nCONFIG pin, while subsequent devices'
nINIT
_CONF pins are left floating.
The INIT_CONF pin has an internal 1-k
pull-up resistor
that is always active in EPC2 devices.
This pin is only available in EPC2 devices.
TDI
N/A
11
13
Input
JTAG data input pin. Connect this pin to VCC if the JTAG
circuitry is not used.
This pin is only available in EPC2 devices.
TDO
N/A
1
28
Output
JTAG data output pin. Do not connect this pin if the JTAG
circuitry is not used.
This pin is only available in EPC2 devices.
TMS
N/A
19
25
Input
JTAG mode select pin. Connect this pin to VCC if the JTAG
circuitry is not used.
This pin is only available in EPC2 devices.
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 2 of 3)
Pin Name
Pin Number
Pin Type
Description
8-Pin
PDIP (1)
20-Pin
PLCC
32-Pin
TQFP (2)
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