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參數(shù)資料
| 型號： | EPC16QI100 |
| 廠商： | Altera |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 100-PQFP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 66 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 16Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1227 |
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Functional Description
Page 19
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
The general guideline for effectiveness of compression is the higher the device logic or
routing utilization, the lower the compression ratio (where the compression ratio is
defined as the original bitstream size divided by the compressed bitstream size).
For Stratix designs, based on a suite of designs with varying amounts of logic
utilization, the minimum compression ratio was observed to be 1.9 or a ~47% size
reduction for these designs. Table 6 lists sample compression ratios from a suite of
Stratix designs. These numbers serve as a guideline, not a specification, to help you
allocate sufficient configuration memory to store compressed bitstreams.
Programmable Configuration Clock
The configuration clock (DCLK) speed is user programmable. One of two clock sources
can be used to synthesize the configuration clock; a programmable oscillator or an
external clock input pin (EXCLK). The configuration clock frequency can be further
synthesized using the clock divider circuitry. This clock can be divided by the N
counter to generate your DCLK output. The N divider supports all integer dividers
between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock
divisions other than non-integer divisions is 50% (for the non-integer dividers, the
duty cycle will not be 50%). Figure 5 shows a block diagram of the clock divider unit.
The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports.
f For more information about the maximum DCLK input frequency supported by the
FPGA, refer to the configuration chapter in the appropriate device handbook.
Table 6. Stratix Compression Ratios (1)
Item
Minimum
Average
Logic Utilization
98%
64%
Compression Ratio
1.9
2.3
% Size Reduction
47%
57%
Note to Table 6:
(1) These numbers are preliminary. They are intended to serve as a guideline, not a specification.
Figure 5. Clock Divider Unit
Configuration Device
Clock Divider Unit
Divide
by N
External Clock
(Up to 100 MHz)
Internal Oscillator
10 MHz
33 MHz
50 MHz
66 MHz
DCLK
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| EPC16QI100N | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16UC88 | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16UC88AA | 功能描述:IC CONFIG DEVICE 16MBIT 88-UBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:EPC 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-TSOP 包裝:管件 |
| EPC16UC88N | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16UI88AA | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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