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參數資料
| 型號： | EPC16QI100N |
| 廠商： | Altera |
| 文件頁數： | 36/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 100-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 66 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 16Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1684 |
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Functional Description
Page 9
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Finally, the configuration controller also manages errors during configuration. A
CONF
_DONE error occurs when the FPGA does not de-assert its CONF_DONE signal within
64 DCLK cycles after the last bit of configuration data is transmitted. When a CONF_DONE
error is detected, the controller pulses the OE line low, which pulls the nSTATUS signal
low and triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in
the configuration data. This corruption could be a result of noise coupling on the
board such as poor signal integrity on the configuration signals. When this error is
signaled by the FPGA (by driving the nSTATUS signal low), the controller stops
configuration. If the Auto-Restart Configuration After Error option is enabled in the
FPGA, it releases its nSTATUS signal after a reset time-out period and the controller
attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives the DCLK pin
low and the DATA[] pins high. Additionally, the controller tri-states its internal
interface to the flash memory, enables the weak internal pull-ups on the flash address
and control lines, and enables bus-keep circuits on flash data lines.
The following sections describe the different configuration schemes supported by the
EPC device—FPP, PS, and concurrent configuration schemes.
f For more information, refer to the configuration chapter in the appropriate device
handbook.
Configuration Signals
Table 4 lists the configuration signal connections between the EPC device and Altera
FPGAs.
Table 4. Configuration Signals
EPC Device Pin
Altera FPGA Pin
Description
DATA[]
Configuration data transmitted from the EPC device to the
FPGA, which is latched on the rising edge of DCLK.
DCLK
EPC device generated clock used by the FPGA to latch
configuration data provided on the DATA[] pins.
nINIT_CONF,
which
nCONFIG
Open-drain output from the EPC device that is used to
start FPGA reconfiguration using the initiate configuration
(INIT_CONF) JTAG instruction. This connection is not
needed if the INIT_CONF JTAG instruction is not needed.
If nINIT_CONF is not connected to nCONFIG, nCONFIG
must be tied to VCC either directly or through a pull-up
resistor.
OE
nSTATUS
Open-drain bidirectional configuration status signal,
which is driven low by either the EPC device or FPGA
during POR and to signal an error during configuration.
Low pulse on OE resets the EPC device controller.
nCS
CONF_DONE
Configuration done output signal driven by the FPGA.
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