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參數資料
| 型號： | EPC16UC88 |
| 廠商： | Altera |
| 文件頁數： | 35/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 88-UBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 105 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 16Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 88-LFBGA |
| 供應商設備封裝： | 88-UBGA（11x8） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1228 |
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Page 8
Functional Description
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
FPGA Configuration
FPGA configuration is managed by the configuration controller chip. This process
includes reading configuration data from the flash memory, decompressing the
configuration data, transmitting configuration data using the appropriate DATA[]
pins, and handling error conditions.
After POR, the controller determines the user-defined configuration options by
reading its option bits from the flash memory. These options include the configuration
scheme, configuration clock speed, decompression, and configuration page settings.
The option bits are stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the internal flash
interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, the configuration controller chip checks if
the FPGA is ready to accept configuration data by monitoring the nSTATUS and
CONF
_DONE signals. When the FPGA is ready (nSTATUS is high and CONF_DONE is low),
the controller begins data transfer using the DCLK and DATA[] output pins. The
controller selects the configuration page to be transmitted to the FPGA by sampling
its PGM[2..0] pins after POR or reset.
The function of the configuration unit is to transmit decompressed data to the FPGA,
depending on the configuration scheme. The EPC device supports four concurrent
configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent
per DCLK cycle on the DATA[n] signals). The value n = 1 corresponds to the traditional
PS configuration scheme. The values n = 2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally,
the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into
the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit
shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[]
pins drive low.
In addition to transmitting configuration data to the FPGAs, the configuration circuit
is also responsible for pausing configuration whenever there is insufficient data
available for transmission. This occurs when the flash read bandwidth is lower than
the configuration write bandwidth. Configuration is paused by stopping the DCLK to
the FPGA, when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing DCLK”.
The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz).
Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps)
(16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported
by Altera FPGAs are much higher and translate to high configuration write
bandwidths. For example, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the
flash memory can support and is the limiting factor for configuration time.
Compression increases the effective flash-read bandwidth as the same amount of
configuration data takes up less space in the flash memory after compression. Since
Stratix configuration data compression ratios are approximately two, the effective
read bandwidth doubles to about 320 Mbps.
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相關代理商/技術參數 |
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|---|---|
| EPC16UC88AA | 功能描述:IC CONFIG DEVICE 16MBIT 88-UBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:EPC 產品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-TSOP 包裝:管件 |
| EPC16UC88N | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16UI88AA | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16UI88N | 功能描述:FPGA-配置存儲器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPC16XXX | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
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