參數(shù)資料
型號(hào)： EPC4QC100
廠商： Altera
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 4MBIT 100-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 66
系列： EPC
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 4Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱： 544-1237
Functional Description
Page 13
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Table 5 lists the concurrent PS configuration modes supported in the EPC device.
f For more information about configuration schematics and concurrent configurations,
refer to the configuration chapter in the appropriate device handbook.
External Flash Interface
The EPC devices support external FPGA or processor access to its flash memory. The
unused portions of the flash memory can be used by the external device to store code
or data. This interface can also be used in systems that implement remote
configuration capabilities. Configuration data within a particular configuration page
can be updated using the external flash interface and the system could be
reconfigured with the new FPGA image. This interface is also useful to store Nios
boot code, application code, or both.
f For more information about the Stratix remote configuration feature, refer to the
Device Handbook.
The address, data, and control ports of the flash memory are internally connected to
the EPC device controller and external device pins. An external source can drive these
external device pins to access the flash memory when the flash interface is available.
This external flash interface is a shared bus interface with the configuration controller
chip. The configuration controller is the primary bus master. Since there is no bus
arbitration support, the external device can only access the flash interface when the
controller has tri-stated its internal interface to the flash. Simultaneous access by the
controller and the external device will cause contention, and result in configuration
and programming failures.
Since the internal flash interface is directly connected to the external flash interface
pins, controller flash access cycles will toggle the external flash interface pins. The
external device must be able to tri-state its flash interface during these operations and
ignore transitions on the flash interface pins.
1 The external flash interface signals cannot be shared between multiple EPC devices
because this causes contention during ISP and configuration. During these operations,
the controller chips inside the EPC devices are actively accessing flash memory.
Therefore, EPC devices do not support shared flash bus interfaces.
Table 5. EPC Devices in PS Mode
Mode Name
Mode (n =) (1)
Used Outputs
Unused Outputs
PS mode
1
DATA0
DATA[7..1]
drive low
Multi-device PS mode
2
DATA[1..0]
DATA[7..2]
drive low
Multi-device PS mode
4
DATA[3..0]
DATA[7..4]
drive low
Multi-device PS mode
8
DATA[7..0]
—
Note to Table 5:
(1) This is the number of valid DATA outputs for each configuration mode.
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