參數(shù)資料
型號： EPF10K100ABI600-2
廠商： Altera
文件頁數(shù)： 38/128頁
文件大?。?/td> 0K
描述： IC FLEX 10KA FPGA 100K 600-BGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 12
系列： FLEX-10K®
LAB/CLB數(shù)： 624
邏輯元件/單元數(shù)： 4992
RAM 位總計： 24576
輸入/輸出數(shù)： 406
門數(shù)： 158000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 600-BGA
供應商設備封裝： 600-BGA（45x45）
Altera Corporation
17
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.7 ns per LE. Cascade
chain logic can be created automatically by the Compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50 device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EAB’s placement in the middle
of the row.
Figure 8 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is as low as 1.6 ns; the
cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is
needed to decode a 16-bit address.
Figure 8. Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n-1)..(4n-4)]
d[3..0]
d[7..4]
d[(4
n-1)..(4n-4)]
LE
n
LE1
LE2
LE
n
LUT
AND Cascade Chain
OR Cascade Chain
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相關代理商/技術參數(shù)
參數(shù)描述
EPF10K100AFC484-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100AFC484-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100AFC484-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100AFC484-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100ARC2401 制造商:ALTERA 功能描述:New
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