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參數(shù)資料
| 型號： | EPF10K100EFC484-1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 39/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 10KE FPGA 100K 484-FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 60 |
| 系列： | FLEX-10KE® |
| LAB/CLB數(shù)： | 624 |
| 邏輯元件/單元數(shù)： | 4992 |
| RAM 位總計： | 49152 |
| 輸入/輸出數(shù)： | 338 |
| 門數(shù)： | 257000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BGA |
| 供應商設備封裝： | 484-FBGA（23x23） |
| 其它名稱： | EPF10K100EFC4841N |
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Altera Corporation
43
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-
V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO
pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 14 summarizes FLEX 10KE MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO.
(2)
When VCCIO = 3.3 V, a FLEX 10KE device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
Open-drain output pins on FLEX 10KE devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin is
inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain
pin will only drive low or tri-state; it will never drive high. The rise time
is dependent on the value of the pull-up resistor and load impedance. The
IOL current specification should be considered when selecting a pull-up
resistor.
Power Sequencing & Hot-Socketing
Because FLEX 10KE devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into FLEX 10KE devices before and during power
up without damaging the device. Additionally, FLEX 10KE devices do not
drive out during power up. Once operating conditions are reached,
FLEX 10KE devices operate as specified by the user.
Table 14. FLEX 10KE MultiVolt I/O Support
VCCIO (V)
Input Signal (V)
Output Signal (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
vv(1)
v(1)
v
3.3
vv
v(1)
v(2)
vv
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K100EFC484-1X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EFC484-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EFC484-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EFC484-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EFC484-2X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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