參數(shù)資料
型號： EPF10K20
廠商： Altera Corporation
英文描述： EMBEDDED PROGRAMMABLE LOGIC FAMILY
中文描述： 嵌入式可編程邏輯系列
文件頁數(shù)： 40/120頁
文件大?。?/td> 1901K
代理商： EPF10K20
26
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode,
the preset signal is tied to VCC to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling the
register preset and clear. LABCTRL2 implements the clear by controlling
the register clear; LABCTRL2 does not have to feed the preset circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting LABCTRL2 presets
the register, while asserting LABCTRL1 loads the register. The
MAX+PLUS II software inverts the signal that drives DATA3 to account for
the inversion of the register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling the
register preset and clear.
相關(guān)PDF資料
PDF描述
EPF10K50 EMBEDDED PROGRAMMABLE LOGIC FAMILY
EP610I Classic EPLD Family
EPF10K130V EMBEDDED PROGRAMMABLE LOGIC FAMILY
EM513 Silicon Rectifiers
EM516 Silicon Rectifiers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K200E 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EPF10K200EBC600-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 1248 LABs 470 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K200EBC600-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 1248 LABs 470 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K200EBC600-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 1248 LABs 470 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K200EBI600-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 1248 LABs 470 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*