參數(shù)資料
型號： EPF10K30ATC144-3
廠商： Altera
文件頁數(shù)： 43/128頁
文件大?。?/td> 0K
描述： IC FLEX 10KA FPGA 30K 144-TQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 180
系列： FLEX-10K®
LAB/CLB數(shù)： 216
邏輯元件/單元數(shù)： 1728
RAM 位總計： 12288
輸入/輸出數(shù)： 102
門數(shù)： 69000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
其它名稱： 544-1264
Altera Corporation
21
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
The Up/down counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. A 2-to-1
multiplexer provides synchronous loading. Data can also be loaded
asynchronously with the clear and preset register control signals, without
using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Clearable counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. Synchronous
loading is provided by a 2-to-1 multiplexer. The output of this multiplexer
is ANDed with a synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1
implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
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相關代理商/技術參數(shù)
參數(shù)描述
EPF10K30ATC144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 216 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K30ATC144-4 制造商:Altera Corporation 功能描述:FLEX10K PLD 10K30 TQFP144 3.3V
EPF10K30ATI144-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 216 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K30ATI144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 216 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K30BC3563 制造商:ALTERA 功能描述:*
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