參數(shù)資料
型號(hào)： EPF6016AQC208-2N
廠商： Altera
文件頁(yè)數(shù)： 9/52頁(yè)
文件大?。?/td> 0K
描述： IC FLEX 6000 FPGA 16K 208-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 144
系列： FLEX 6000
LAB/CLB數(shù)： 132
邏輯元件/單元數(shù)： 1320
輸入/輸出數(shù)： 171
門數(shù)： 16000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Altera Corporation
17
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 8. LE Clear & Preset Modes
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2.
Asynchronous Preset
An asynchronous preset is implemented with an asynchronous clear. The
Altera software provides preset control by using the clear and inverting
the input and output of the register. Inversion control is available for the
inputs to both LEs and IOEs. Therefore, this technique can be used when
a register drives logic or drives a pin.
In addition to the two clear and preset modes, FLEX 6000 devices provide
a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device.
The option to use this pin is set in the Altera software before compilation.
The chip-wide reset overrides all other control signals. Any register with
an asynchronous preset will be preset when the chip-wide reset is asserted
because of the inversion technique used to implement the asynchronous
preset.
The Altera software can use a programmable NOT-gate push-back
technique to emulate simultaneous preset and clear or asynchronous load.
However, this technique uses an additional three LEs per register.
FastTrack Interconnect
In the FLEX 6000 OptiFLEX architecture, connections between LEs and
device I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
device. This global routing structure provides predictable performance,
even for complex designs. In contrast, the segmented routing in FPGAs
requires switch matrices to connect a variable number of routing paths,
increasing the delays between logic resources and reducing performance.
PRN
DQ
labctrl1 or
labctrl2
Asynchronous Clear
Asynchronous Preset
CLRN
DQ
Chip-Wide Reset
labctrl1 or
labctrl2
Chip-Wide Reset
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF6016AQC208-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6016AQC208-3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6016AQI208-2 功能描述:IC FLEX 6000 FPGA 16K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:FLEX 6000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
EPF6016AQI2083 制造商:ALTERA 功能描述:New
EPF6016AQI208-3 制造商:Rochester Electronics LLC 功能描述:- Bulk
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