參數(shù)資料
型號： EPF6024AQC208-2
廠商： Altera
文件頁數(shù)： 46/52頁
文件大?。?/td> 0K
描述： IC FLEX 6000 FPGA 24K 208-PQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 144
系列： FLEX 6000
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 1960
輸入/輸出數(shù)： 171
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-PQFP（28x28）
其它名稱： 544-1284
50
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Operating Modes
The FLEX 6000 architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers
up. This process of physically loading the SRAM data into a FLEX
6000 device is known as configuration. During initialization—a
process that occurs immediately after configuration—the device
resets registers, enables I/O pins, and begins to operate as a logic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. The configuration and initialization processes
of a device are referred to as command mode; normal device operation
is called user mode.
SRAM configuration elements allow FLEX 6000 devices to be
reconfigured in-circuit by loading new configuration data into the
device. Real-time reconfiguration is performed by forcing the device
into command mode with a device pin, loading different
configuration data, reinitializing the device, and resuming user-
mode operation. The entire reconfiguration process requires less
than 100 ms and is used to dynamically reconfigure an entire system.
Also, in-field system upgrades can be performed by distributing new
configuration files.
Configuration Schemes
The configuration data for a FLEX 6000 device can be loaded with
one of three configuration schemes, which is chosen on the basis of
the target application. An EPC1 or EPC1441 configuration device or
intelligent controller can be used to control the configuration of a
FLEX 6000 device, allowing automatic configuration on system
power-up.
Multiple FLEX 6000 devices can be configured in any of the three
configuration schemes by connecting the configuration enable input
(nCE) and configuration enable output (nCEO) pins on each device.
Table 40 shows the data sources for each configuration scheme.
Table 40. Configuration Schemes
Configuration Scheme
Data Source
Configuration device
EPC1 or EPC1441 configuration device
Passive serial (PS)
BitBlaster
TM, ByteBlasterMVTM, or MasterBlasterTM
download cables, or serial data source
Passive serial asynchronous
(PSA)
BitBlaster, ByteBlasterMV, or MasterBlaster
download cables, or serial data source
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相關代理商/技術參數(shù)
參數(shù)描述
EPF6024AQC208-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC240-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC240-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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