參數(shù)資料
型號： EPF8282ALC84-4
廠商： Altera
文件頁數(shù)： 17/62頁
文件大?。?/td> 0K
描述： IC FLEX 8000A FPGA 2.5K 84-PLCC
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 75
系列： FLEX 8000
LAB/CLB數(shù)： 26
邏輯元件/單元數(shù)： 208
輸入/輸出數(shù)： 68
門數(shù)： 2500
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.31x29.31）
產(chǎn)品目錄頁面： 602 (CN2011-ZH PDF)
其它名稱： 544-2251-5
24
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
MultiVolt I/O Interface
The FLEX 8000 device architecture supports the MultiVolt I/O interface
feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A
devices to interface with systems with differing supply voltages. These
devices in all packages—except for EPF8636A devices in 84-pin PLCC
packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply. With
a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore
compatible with 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V
incur a nominally greater timing delay of tOD2 instead of tOD1. See Table 8
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A
devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG
circuitry support the JTAG instructions shown in Table 6.
Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation.
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參數(shù)描述
EPF8282ALC84-4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC100-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC100-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC100-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC100-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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