參數(shù)資料
型號: EPF8452ALC84-4
廠商: Altera
文件頁數(shù): 1/62頁
文件大?。?/td> 0K
描述: IC FLEX 8000A FPGA 4K 84-PLCC
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 75
系列: FLEX 8000
LAB/CLB數(shù): 42
邏輯元件/單元數(shù): 336
輸入/輸出數(shù): 68
門數(shù): 4000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 84-LCC(J 形引線)
供應商設(shè)備封裝: 84-PLCC(29.31x29.31)
產(chǎn)品目錄頁面: 602 (CN2011-ZH PDF)
其它名稱: 544-2257-5
Altera Corporation
1
FLEX 8000
Programmable Logic
Device Family
January 2003, ver. 11.1
Data Sheet
DS-F8000-11.1
FL
EX
800
0
3
1
Features...
Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
2,500 to 16,000 usable gates
282 to 1,500 registers
System-level features
In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
–MultiVoltTM I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
Low power consumption (typical specification is 0.5 mA or less in
standby mode)
Flexible interconnect
–FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state nets
Powerful I/O pins
Programmable output slew-rate control reduces switching noise
Table 1. FLEX 8000 Device Features
Feature
EPF8282A
EPF8282AV
EPF8452A
EPF8636A
EPF8820A
EPF81188A EPF81500A
Usable gates
2,500
4,000
6,000
8,000
12,000
16,000
Flipflops
282
452
636
820
1,188
1,500
Logic array blocks (LABs)
26
42
63
84
126
162
Logic elements (LEs)
208
336
504
672
1,008
1,296
Maximum user I/O pins
78
120
136
152
184
208
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