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參數(shù)資料
| 型號： | EPF8452AQC160-4 |
| 廠商： | Altera |
| 文件頁數(shù)： | 5/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 8000A FPGA 4K 160-PQFP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 72 |
| 系列： | FLEX 8000 |
| LAB/CLB數(shù)： | 42 |
| 邏輯元件/單元數(shù)： | 336 |
| 輸入/輸出數(shù)： | 120 |
| 門數(shù)： | 4000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-PQFP（28x28） |
| 產(chǎn)品目錄頁面： | 602 (CN2011-ZH PDF) |
| 其它名稱： | 544-2259 |
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Altera Corporation
13
FLEX 8000 Programmable Logic Device Family Data Sheet
FL
EX
800
0
3
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable signals select the signal that drives the bus.
However, if multiple output enable signals are active, contending signals
can be driven onto the bus. Conversely, if no output enable signals are
active, the bus will float. Internal tri-state emulation resolves contending
tri-state buffers to a low value and floating buses to a high value, thereby
eliminating these problems. The MAX+PLUS II software automatically
implements tri-state bus functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE is used to asynchronously load
signals into a register. The register can be set up so that LABCTRL1
implements an asynchronous load. The data to be loaded is driven to
DATA3
; when LABCTRL1 is asserted, DATA3 is loaded into the register.
During compilation, the MAX+PLUS II Compiler automatically selects
the best control signal implementation. Because the clear and preset
functions are active-low, the Compiler automatically assigns a logic high
to an unused clear or preset.
The clear and preset logic is implemented in one of the following six
asynchronous modes, which are chosen during design entry. LPM
functions that use registers will automatically use the correct
asynchronous mode. See Figure 7.
■
Clear only
■
Preset only
■
Clear and preset
■
Load with clear
■
Load with preset
■
Load without clear or preset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8452AQC160-4N | 制造商:Altera Corporation 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 160-Pin PQFP |
| EPF8452AQC160-5 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 160 Pin, Plastic, QFP |
| EPF8452AQC160-6 | 制造商:Altera Corporation 功能描述: |
| EPF8452AQI160-3 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 160 Pin, Plastic, QFP |
| EPF8452ATC100-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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