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參數(shù)資料
| 型號： | EPM240GT100I5 |
| 廠商： | Altera |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 0K |
| 描述： | IC MAX II CPLD 240 LE 100-TQFP |
| 產(chǎn)品變化通告： | Bond Wire Change 4/Sept/2008 |
| 標準包裝： | 270 |
| 系列： | MAX® II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.7ns |
| 電壓電源 - 內(nèi)部： | 1.71 V ~ 1.89 V |
| 邏輯元件/邏輯塊數(shù)目： | 240 |
| 宏單元數(shù)： | 192 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 603 (CN2011-ZH PDF) |
| 其它名稱： | 544-2274 |
Chapter 1: Introduction
1–3
Features
MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA,
and thin quad flat pack (TQFP) packages (refer to Table 1–3 and Table 1–4). MAX II
devices support vertical migration within the same package (for example, you can
migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin
FineLine BGA package). Vertical migration means that you can migrate to devices
whose dedicated pins and JTAG pins are the same and power pins are subsets or
supersets for a given package across device densities. The largest density in any
package has the highest number of power pins; you must lay out for the largest
planned density in a package to provide the necessary power pins for migration. For
I/O pin migration across densities, cross reference the available I/O pins using the
device pin-outs for all planned densities of a given package type to identify which
I/O pins can be migrated. The Quartus II software can automatically cross-reference
and place all pins for you when given a device migration list.
Table 1–3. MAX II Packages and User I/O Pins
Device
68-Pin
Micro
FineLine
BGA (1)
100-Pin
Micro
FineLine
BGA (1)
100-Pin
FineLine
BGA
100-Pin
TQFP
144-Pin
TQFP
144-Pin
Micro
FineLine
BGA (1)
256-Pin
Micro
FineLine
BGA (1)
256-Pin
FineLine
BGA
324-Pin
FineLine
BGA
EPM240
EPM240G
—80
80
—
EPM570
EPM570G
—
76
116
—
160
—
EPM1270
EPM1270G
—
116
—
212
—
EPM2210
EPM2210G
—
——
—204
272
EPM240Z
54
80
—
EPM570Z
—
76
—
116
160
—
Note to Table 1–3:
(1) Packages available in lead-free versions only.
Table 1–4. MAX II TQFP, FineLine BGA, and Micro FineLine BGA Package Sizes
Package
68-Pin
Micro
FineLine
BGA
100-Pin
Micro
FineLine
BGA
100-Pin
FineLine
BGA
100-Pin
TQFP
144-Pin
TQFP
144-Pin
Micro
FineLine
BGA
256-Pin
Micro
FineLine
BGA
256-Pin
FineLine
BGA
324-Pin
FineLine
BGA
Pitch (mm)
0.5
1
0.5
1
Area (mm2)
25
36
121
256
484
49
121
289
361
Length × width
(mm × mm)
5 × 5
6 × 6
11 × 11
16 × 16
22 × 22
7 × 7
11 × 11
17 × 17
19 × 19
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM240GT100I5N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 192 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM240GT100I5NRR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP |
| EPM240GT100I5RR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP |
| EPM240M100A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM240M100C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
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