參數(shù)資料
型號: EPM3128ATC100-5
廠商: Altera
文件頁數(shù): 12/46頁
文件大?。?/td> 0K
描述: IC MAX 3000A CPLD 128 100-TQFP
產(chǎn)品變化通告: Bond Wire Change 4/Sept/2008
標準包裝: 270
系列: MAX® 3000A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 128
門數(shù): 2500
輸入/輸出數(shù): 80
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 603 (CN2011-ZH PDF)
其它名稱: 544-1164
2
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
PCI compatible
Bus–friendly architecture including programmable slew–rate control
Open–drain output option
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power–saving mode for a power reduction of over
50% in each macrocell
Configurable expander product–term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
Enhanced architectural features, including:
6 or 10 pin– or logic–driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Programmable output slew–rate control
Software design support and automatic place–and–route provided
by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with the Altera master programming unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from third–party manufacturers and
any in–circuit tester that supports JamTM Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low–cost, high–performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM–based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
. See Table 2.
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