Notes to tables: (1) These values are specified under the recommende" />
參數(shù)資料
型號(hào): EPM7032LC44-15T
廠商: Altera
文件頁(yè)數(shù): 43/66頁(yè)
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 32 44-PLCC
產(chǎn)品變化通告: MAX 7000 Series Obsolescence 08/Jun/2009
標(biāo)準(zhǔn)包裝: 390
系列: MAX® 7000
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門(mén)數(shù): 600
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
其它名稱(chēng): 544-2287-5
48
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
The fMAX values represent the highest frequency for pipelined data.
(6)
Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in the low-power mode.
Tables 35 and 36 show the EPM7192S AC operating conditions.
tCLR
Register clear time
2.4
3.0
4.0
ns
tPIA
PIA delay
1.6
2.0
1.0
2.0
ns
tLPA
Low-power adder
11.0
10.0
11.0
13.0
ns
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min
Max
Min
Max
Min
Max
Min
Max
Table 35. EPM7192S External Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
tPD1
Input to non-registered output
C1 = 35 pF
7.5
10.0
15.0
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF
7.5
10.0
15.0
ns
tSU
Global clock setup time
4.1
7.0
11.0
ns
tH
Global clock hold time
0.0
ns
tFSU
Global clock setup time of fast
input
3.0
ns
tFH
Global clock hold time of fast
input
0.0
0.5
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
4.7
5.0
8.0
ns
tCH
Global clock high time
3.0
4.0
5.0
ns
tCL
Global clock low time
3.0
4.0
5.0
ns
tASU
Array clock setup time
1.0
2.0
4.0
ns
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EPM7032LC44-2 制造商:Altera Corporation 功能描述:
EPM7032LC44-3 制造商:Altera Corporation 功能描述:
EPM7032LC446 制造商:ALTERA 功能描述:*
EPM7032LC44-6 功能描述:IC MAX 7000 CPLD 32 44-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:MAX® 7000 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28) 包裝:托盤(pán)
EPM7032LC447 制造商:ALTERA 功能描述:*