參數(shù)資料
型號： EPM7128ALC84-12
文件頁數(shù)： 44/60頁
文件大?。?/td> 1030K
代理商： EPM7128ALC84-12
Altera Corporation
49
MAX 7000A Programmable Logic Device Data Sheet
Table 27. EPM7256A Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min
Max
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.3
0.4
0.5
0.6
ns
tIO
I/O input pad and buffer
delay
0.3
0.4
0.5
0.6
ns
tFIN
Fast input delay
2.4
3.0
3.4
3.8
ns
tSEXP
Shared expander delay
2.8
3.5
4.7
5.6
ns
tPEXP
Parallel expander delay
0.5
0.6
0.8
1.0
ns
tLAD
Logic array delay
2.5
3.1
4.2
5.0
ns
tLAC
Logic control array delay
2.5
3.1
4.2
5.0
ns
tIOE
Internal output enable
delay
0.2
0.3
0.4
0.5
ns
tOD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.3
0.4
0.5
0.6
ns
tOD2
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
0.8
0.9
1.0
1.1
ns
tOD3
Output buffer and pad
delay slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
5.3
5.4
5.5
5.6
ns
tZX1
Output buffer enable
delay slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
4.0
5.0
ns
tZX2
Output buffer enable
delay slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
4.5
5.5
ns
tZX3
Output buffer enable
delay slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
9.0
10.0
ns
tXZ
Output buffer disable
delay
C1 = 5 pF
4.0
5.0
ns
tSU
Register setup time
1.0
1.3
1.7
2.0
ns
tH
Register hold time
1.7
2.4
3.7
4.7
ns
tFSU
Register setup time of fast
input
1.2
1.4
ns
tFH
Register hold time of fast
input
1.3
1.6
ns
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