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| 型號： | EPM7128ATC100-10 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大小： | 1030K |
| 代理商： | EPM7128ATC100-10 |
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Altera Corporation
17
MAX 7000A Programmable Logic Device Data Sheet
f For more information on using the Jam STAPL language, see Application
ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming
with External
Hardware
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checks to ensure adequate
electrical contact between the adapter and the device.
f For more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices.
f For more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1. Table 5 describes the JTAG instructions supported by MAX 7000A
devices. The pin-out tables, available from the Altera web site
(http://www.altera.com), show the location of the JTAG control pins for
each device. If the JTAG interface is not required, the JTAG pins are
available as user I/O pins.
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| EPM7128ATC100-10F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7128ATC100-12 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 128-CELL, 12NS PROP DELAY, 100 Pin, Plastic, TQFP |
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| EPM7128ATC1006 | 制造商:ALTERA 功能描述:* |
| EPM7128ATC100-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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