f For more information on using " />
參數(shù)資料
型號(hào)： EPM7192SQI160-10
廠商： Altera
文件頁(yè)數(shù)： 9/66頁(yè)
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 192 160-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： MAX® 7000
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目： 12
宏單元數(shù)： 192
門(mén)數(shù)： 3750
輸入/輸出數(shù)： 124
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱(chēng)： 544-2343
Altera Corporation
17
MAX 7000 Programmable Logic Device Family Data Sheet
f For more information on using the Jam language, refer to AN 122: Using
Jam STAPL for ISP & ICR via an Embedded Processor.
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000S device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7192SQI160-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7256 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
EPM7256A 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Programmable Logic Device
EPM7256AE 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Programmable Logic Device
EPM7256AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 256 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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