VDD = 5 V ± 10% or 3 V ± 10%, V" />
參數(shù)資料
型號： EVAL-AD5245EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/20頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR AD5245
標(biāo)準(zhǔn)包裝： 1
主要目的： 數(shù)字電位器
嵌入式： 否
已用 IC / 零件： AD5245
主要屬性： 1 通道，256 位置
次要屬性： I²C 接口
已供物品： 板
AD5245
Rev. B | Page 4 of 20
10 k, 50 k, 100 k VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
–1
±0.1
+1
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
–2
±0.25
+2
LSB
Nominal Resistor Tolerance3
RAB
TA = 25°C
–30
+30
%
Resistance Temperature Coefficient
(RAB/RAB)/T × 106
VAB = VDD, wiper = no connect
45
ppm/°C
Wiper Resistance
RW
VDD = 5 V
50
120
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
DNL
–1
±0.1
+1
LSB
Integral Nonlinearity4
INL
–1
±0.3
+1
LSB
Voltage Divider Temperature Coefficient
(VW/VW)/T × 106
Code = 0x80
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0xFF
–3
–1
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
1
3
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
GND
VDD
V
Capacitance A, B6
CA, CB
f = 1 MHz, measured to GND,
code = 0x80
90
pF
Capacitance W6
CW
f = 1 MHz, measured to GND,
code = 0x80
95
pF
Shutdown Supply Current
IA_SD
VDD = 5.5 V
0.01
1
A
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
2.4
V
Input Logic Low
VIL
VDD = 5 V
0.8
V
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
A
Input Capacitance6
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3
8
A
Power Dissipation7
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
44
W
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%,
code = midscale
±0.02
±0.05
%/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
BW
RAB = 10 k/50 k/100 k,
code = 0x80
600/100/40
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 k
0.1
%
VW Settling Time (10 k/50 k/100 k)
tS
VA = 5 V, VB = 0 V,
±1 LSB error band
2
s
Resistor Noise Voltage Density
eN_WB
RWB = 5 k, RS = 0
9
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
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