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| 型號： | EVAL-AD5259DBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5259DBZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
AD5259
Data Sheet
Rev. C | Page 16 of 24
I2C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control
registers for the AD5259 all refer to the device addresses listed
in Table 5; the mode/condition reference key (S, P, SA, MA,
NA, W, R, and X) is listed below.
S = Start Condition
P = Stop Condition
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
W = Write
R = Read
X = Don’t Care
AD1 and AD0 are two-state address pins.
Table 5. Device Address Lookup
AD1 Address Pin
AD0 Address Pin
I2C Device Address
0
0011000
1
0
0011010
0
1
1001100
1
1001110
GENERIC INTERFACE
Table 6. Generic Interface Format
S
7-Bit Device Address
(See Table 5)
R/W
SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte
Instruction Byte
Data Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2
C1
C0
Command Description
0
Operation Between Interface and RDAC.
0
1
Operation Between Interface and EEPROM.
0
1
0
Operation Between Interface and Write Protection Register. See Table 10.
1
0
NOP.
1
0
1
Restore EEPROM to RDAC.1
1
0
Store RDAC to EEPROM.
1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
WRITE MODES
Table 8. Writing to RDAC Register
S
7-Bit Device Address
0
SA 0
0
SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte
Instruction Byte
Data Byte
Table 9. Writing to EEPROM Register
S
7-Bit Device Address
0
SA 0
0
1
0
SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte
Instruction Byte
Data Byte
Table 10. Activating/Deactivating Software Write Protect
S
7-Bit Device Address
0
SA 0
1
0
SA 0
0
WP SA P
Slave Address Byte
Instruction Byte
Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the
command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
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