參數(shù)資料
型號(hào)： EVAL-AD5363EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 17/29頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD5363
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 8
位數(shù)： 14
采樣率（每秒）： 540k
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 20µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5363
相關(guān)產(chǎn)品： AD5363BSTZ-REEL-ND - IC DAC 14BIT 8CH SERIAL 52-LQFP
AD5363BSTZ-ND - IC DAC 14BIT 8CH SERIAL 52-LQFP
AD5363BCPZ-REEL7-ND - IC DAC 14BIT 8CH SERIAL 56-LFCSP
AD5363BCPZ-ND - IC DAC 14BIT 8CH SERIAL 56-LFCSP
AD5362/AD5363
Rev. A | Page 23 of
28
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5362/AD5363 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5362/AD5363 should generate an 8-bit
checksum using the polynomial C(x) = x8 + x2 + x1 + 1. This is
added to the end of the data-word, and 32 data bits are sent to
the AD5362/AD5363 before taking SYNC high. If the AD5362/
AD5363 see a 32-bit data frame, an error check is performed
when SYNC goes high. If the checksum is valid, the data is
written to the selected register. If the checksum is invalid, the
packet error check (PEC) output goes low and Bit 3 of the
control register is set. After reading the control register, Bit 3
is cleared automatically and PEC goes high again.
SYNC
SCLK
SDI
24-BIT DATA TRANSFER—NO ERROR CHECKING
SYNC
SCLK
SDI
MSB
D23
LSB
D0
MSB
D31
LSB
D8
D7
D0
UPDATE ON SYNC HIGH
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
24-BIT DATA
24-BIT DATA TRANSFER WITH ERROR CHECKING
8-BIT FCS
PEC
PEC GOES LOW IF
ERROR CHECK FAILS
05
76
2-
02
6
Figure 24. SPI Write With and Without Error Checking
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D15 to D0 (AD5362)
or D13 to D0 (AD5363) is written to the device. Address Bit A4
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in Table 13 and Table 14. Data is to
be written to the X1A register when the A/B bit in the control
register is 0, or to the X1B register when the A/B bit is 1.
The AD5362/AD5363 have very flexible addressing that allows
the writing of data to a single channel, all channels in a group,
or all channels in the device.
Table 14 shows which groups and which channels are addressed
for every combination of Address Bit A4 to Address Bit A0.
Table 13. Mode Bits
M1
M0
Action
1
Write to DAC data (X) register
1
0
Write to DAC offset (C) register
0
1
Write to DAC gain (M) register
0
Special function, used in combination with other
bits of the data-word
Table 14. Group and Channel Addressing
Address Bit A2
to Address Bit A0
Address Bit A4 to Address Bit A3
00
01
10
11
000
All groups, all channels
Group 0, Channel 0
Group 1, Channel 0
Unused
001
Group 0, all channels
Group 0, Channel 1
Group 1, Channel 1
Unused
010
Group 1, all channels
Group 0, Channel 2
Group 1, Channel 2
Unused
011
Unused
Group 0, Channel 3
Group 1, Channel 3
Unused
100
Unused
101
Unused
110
Unused
111
Unused
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