Test Conditions/Comments
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EVAL-AD5373EBZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 26/29闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� BOARD EVAL FOR AD5373
鐢㈠搧鍩硅〒妯″锛� DAC Architectures
妯欐簴鍖呰锛� 1
DAC 鐨勬暩(sh霉)閲忥細 32
浣嶆暩(sh霉)锛� 14
閲囨ǎ鐜囷紙姣忕锛夛細 540k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
瑷疆鏅傞枔锛� 20µs
DAC 鍨嬶細 闆诲
宸ヤ綔婧害锛� -40°C ~ 85°C
宸蹭緵鐗╁搧锛� 鏉�锛孋D
宸茬敤 IC / 闆朵欢锛� AD5373
AD5372/AD5373
Rev. C | Page 5 of 28
Parameter
AD53721
B Version
AD53731
B Version
Unit
Test Conditions/Comments2
POWER REQUIREMENTS
DVCC
2.5/5.5
V min/V max
VDD
9/16.5
V min/V max
VSS
16.5/4.5
V min/V max
Power Supply Sensitivity2
Full Scale/VDD
75
dB typ
Full Scale/VSS
75
dB typ
Full Scale/DVCC
90
dB typ
DICC
2
mA max
DVCC = 5.5 V, VIH = DVCC, VIL = GND
IDD
16
mA max
Outputs unloaded, DAC outputs = 0 V
18
mA max
Outputs unloaded, DAC outputs = full scale
ISS
16
mA max
Outputs unloaded, DAC outputs = 0 V
18
mA max
Outputs unloaded, DAC outputs = full scale
Power-Down Mode
Bit 0 in the control register is 1
DICC
5
渭A typ
IDD
35
渭A typ
ISS
35
渭A typ
Power Dissipation (Unloaded)
250
mW typ
VSS = 8 V, VDD = 9.5 V, DVCC = 2.5 V
Junction Temperature3
130
掳C max
TJ = TA + PTOTAL 脳 胃JA
1 Temperature range for B version: 40掳C to +85掳C. Typical specifications are at 25掳C.
2 Guaranteed by design and characterization; not production tested.
3 JA represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = 15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 k惟; gain (M),
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
渭s typ
Full-scale change
30
渭s max
DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate
1
V/渭s typ
Digital-to-Analog Glitch Energy
5
nV-s typ
Glitch Impulse Peak Amplitude
10
mV max
Channel-to-Channel Isolation
100
dB typ
VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk
10
nV-s typ
Digital Crosstalk
0.2
nV-s typ
Digital Feedthrough
0.02
nV-s typ
Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz
250
nV/鈭欻z typ
VREF0 = VREF1 = 0 V
1 Guaranteed by design and characterization; not production tested.
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