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參數(shù)資料
| 型號(hào)： | EVAL-AD5382EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5382 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 32 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | DSP，I²C，MICROWIRE?，并行，QSPI?，SPI? |
| 設(shè)置時(shí)間： | 8µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5382 |
| 其它名稱： | Q4391457 |
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AD5382
Data Sheet
Rev. C | Page 16 of 40
Mnemonic
Function
PD
Power Down (Level Sensitive, Active High). PD is used to place the device in to low power mode where the device
consumes 2 A AIDD and 20 A DIDD. In power-down mode, all internal analog circuitry is placed in low power
mode, and the analog output is configured as a high impedance output or provides a 100 k load to ground,
depending on how the power-down mode is configured. The serial interface remains active during power-down.
FIFO EN
FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user
to write to the device at full speed. FIFO is available only in parallel interface mode. The status of the FIFO EN pin is
sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I2C
interface modes, the FIFO EN pin should be tied low.
DB11/(SPI/I2C)
Multifunction Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. In serial
interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and
this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB13 is the serial data
(DIN) input.
When serial interface mode is selected (SER/PAR = 1) and this input is high, I2C mode is selected. In this mode, DB12
is the serial clock (SCL) input and DB13 is the serial data (SDA) input.
DB12/(SCLK/SCL)
Multifunction Input Pin. In parallel interface mode, this pin acts as DB12 of the parallel input data-word. In serial
interface mode, this pin acts as a serial clock input.
Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This
operates at clock speeds up to 50 MHz.
I2C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C
mode is compatible with both 100 kHz and 400 kHz operating modes.
DB13/(DIN/SDA)
Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB13 of the parallel input data-word.
Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling
edge of SCLK.
I2C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.
NC
No Connect. The user is advised not to connect any signals to these pins.
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