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參數資料
| 型號： | EVAL-AD5570SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5570 |
| 標準包裝： | 1 |
| DAC 的數量： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 83k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 設置時間： | 12µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5570 |
AD5570
Rev. C | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VSS 1
VDD 2
CLR 3
LDAC 4
SYNC 5
SCLK 6
SDIN 7
SDO 8
REFGND
REFIN
REFGND
VOUT
AGNDS
16
15
14
13
12
AGND
PD
DGND
11
10
9
AD5570
TOP VIEW
(Not to Scale)
03760-005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VSS
Negative Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
2
VDD
Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
3
CLR
Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to AGND. The contents of the registers
are untouched.
4
LDAC
Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC can be tied
permanently low, enabling the outputs to be updated on the rising edge of SYNC.
5
SYNC
Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers
on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of
the following 16 clocks.
6
SCLK
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 8 MHz.
7
SDIN
Serial Data Input. Data is clocked into the 16-bit register on the falling edge of the serial clock input.
8
SDO
Serial Data Output. Can be used for daisy-chaining a number of devices together or for reading back the data in
the shift register for diagnostic purposes. This is an open-drain output; it must be pulled to logic high with an
external pull-up resistor of ~5 kΩ.
9
DGND
Digital Ground. Ground reference for all digital circuitry.
10
PD
Active Low Control Input. Allows the DAC to be put into a power-down state.
11
AGND
Analog Ground. Ground reference for all analog circuitry.
12
AGNDS
Analog Ground Sense. This is normally tied to AGND.
13
VOUT
Analog Output Voltage.
14, 16
REFGND
Reference Ground. Tie this pin to 0 V.
15
REFIN
Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output
range, REFIN is 5 V.
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