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參數(shù)資料
| 型號(hào)： | EVAL-AD5669REBRZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5669 TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | denseDAC |
| DAC 的數(shù)量： | 8 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 設(shè)置時(shí)間： | 2.5µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5669 |
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Data Sheet
AD5629R/AD5669R
Rev. D | Page 23 of 32
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19
9
1
SCL
START BY
MASTER
ACK. BY
AD5629R/AD5669R
ACK. BY
MASTER
SDA
R/W
DB23
A0
A1
1
0
1
0
DB22 DB21
DB20
DB19 DB18
DB17
DB16
19
9
1
ACK. BY
MASTER
NO ACK.
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
STOP BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14
DB13 DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
08
81
9
-04
9
Figure 52. I2C Read Operation
Table 8. Command Definitions
Command
C3
C2
C1
C0
Description
0
Write to Input Register n
0
1
Update DAC Register n
0
1
0
Write to Input Register n; update all
(software LDAC)
0
1
Write to and update DAC Channel n
0
1
0
Power down/power up DAC
0
1
0
1
Load clear code register
0
1
0
Load LDAC register
0
1
Reset (power-on reset)
1
0
Set up internal REF register
1
0
1
Enable multiple byte mode
1
0
1
0
Reserved
–
Reserved
1
Reserved
Table 9. Address Commands
Address (n)
A3
A2
A1
A0
Selected DAC Channel
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
0
1
0
DAC E
0
1
0
1
DAC F
0
1
0
DAC G
0
1
DAC H
1
All DACs
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The input register contents for this operation is shown in
Figure 53 and Figure 54. The eight MSBs make up the command
byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0,
that control the mode of operation of the device (see Table 9 for
details). The last four bits of the first byte are the address bits,
A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits
are the 16-/12-bit data-word.
The AD5669R data-word comprises the 16-bit input code (see
Figure 53) while the AD5629R data word is comprised of 12-
bits followed by four don’t cares (see Figure 54).
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD5629R/AD5669R.
Command 1001 is reserved for multiple byte operation (see
Table 8) A 2-byte operation is useful for applications that
require fast DAC updating and do not need to change the
command byte. The S bit (DB22) in the command register
can be set to 1 for the 2-byte mode of operation. For standard
3-byte and 4-byte operation, the S bit (DB22) in the command
byte should be set to 0.
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