參數(shù)資料
型號(hào)： EVAL-AD5764REBZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/32頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR AD5764
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
設(shè)置時(shí)間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5764R
Data Sheet
AD5764R
Rev. D | Page 23 of 32
See Figure 41 for a simplified block diagram of the DAC load
circuitry.
VOUTx
DATA
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
REFAB, REFCD
SYNC
INPUT
REGISTER
SCLK
06064-
062
Figure 41. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
The output voltage expression for the AD5764R is given by
×
+
×
=
536
,
65
4
2
D
V
REFIN
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB and
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time for the operation to complete
(see Figure 2). When the CLR signal is returned high, the output
remains at the cleared value until a new value is programmed.
If CLR is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
Digital Input
Analog Output
MSB
LSB
VOUT
1111
+2 VREFIN × (32,767/32,768)
1000
0000
0001
+2 VREFIN × (1/32,768)
1000
0000
0 V
0111
1111
2 VREFIN × (1/32,768)
0000
2 VREFIN × (32,767/32,768)
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
Digital Input
Analog Output
MSB
LSB
VOUT
0111
1111
+2 VREFIN × (32,767/32,768)
0000
0001
+2 VREFIN × (1/32,768)
0000
0 V
1111
2 VREFIN × (1/32,768)
1000
0000
2 VREFIN × (32,767/32,768)
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