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參數(shù)資料
| 型號： | EVAL-AD7171EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7171 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7171 |
| 已供物品： | 板 |
Data Sheet
AD7171
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
SCLK
2
DOUT/RDY
3
AIN(+)
4
AIN(–)
5
REFIN(+)
10 NC
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GROUND.
9 PDRST
8VDD
7GND
6REFIN(–)
AD7171
TOP VIEW
(Not to Scale)
08
41
7-
00
5
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered
input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it
can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data.
2
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready
pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to
access the data register of the ADC. Eight status bits accompany each data read. See Figure 13 for further details.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If
the data is not read after the conversion, the pin goes high before the next update occurs.
3
AIN(+)
Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN().
4
AIN()
Analog Input. AIN() is the negative terminal of the dierential analog input pair AIN(+)/AIN().
5
REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal
reference voltage (REFIN(+) – REFIN()) is 5 V, but the part can function with a reference of 0.5 V to VDD.
6
REFIN()
Negative Reference Input.
7
GND
Ground Reference Point.
8
VDD
Supply Voltage, 2.7 V to 5.25 V.
9
PDRST
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is
reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The
on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms
approximately to power up.
10
NC
This pin should be connected to GND for correct operation.
EPAD
Connect the exposed pad to ground.
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