- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17057 > EVAL-AD7191EBZ (Analog Devices Inc)BOARD EVAL FOR AD7191 PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD7191EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7191 |
| 設(shè)計(jì)資源： | EVAL-AD7191 Schematic AD7191 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±5 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7191 |
| 已供物品： | 板 |
AD7191
Rev. A | Page 14 of 20
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7191 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit, Σ-Δ ADC, a PGA, and an on-chip digital filter intended
for measuring wide dynamic range signals.
The device has an internal clock and two differential analog
inputs. It offers a choice of four output data rates (10 Hz, 50 Hz,
60 Hz, and 120 Hz) and four gain settings (1, 8, 64, and 128).
The device also has an internal temperature sensor. These
functions are controlled using dedicated pins, which make the
interface easy to configure. A 2-wire interface simplifies data
retrieval from the AD7191.
FILTER, DATA RATE, AND SETTLING TIME
The AD7191 has four output data rates, which are selected
using the ODR2 and ODR1 pins (see Table 5). When the
polarity of ODR2 or ODR1 is changed, the AD7191 modulator
and filter are reset immediately. DOUT/RDY is set high, and
the ADC then begins conversions using the selected output data
rate. The first conversion requires the complete settling time of
the filter. Subsequent conversions occur at the selected output
data rate. The settling time of the digital filter, tSETTLE, is
tSETTLE = 4/Output Data Rate
That is, the settling time is equal to four conversion cycles.
When a step change occurs on the analog input, the AD7191
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period
(see Figure 17), then to generate a valid conversion, the settling
time of the AD7191 must be allowed. If the step change occurs
asynchronous to the end of a conversion (see Figure 18), then to
generate a valid conversion, an extra conversion period must be
allowed. The diagrams show the case for an output data rate of
50 Hz; therefore, an asynchronous step change can increase the
time to generate a valid conversion by 20 ms. The data register
is updated with all the conversions but, for an accurate result,
the user must allow the required time.
ANALOG INPUT
ADC OUTPUT
0ms
20ms
40ms
60ms
80ms
100ms
VALID
08
16
3-
0
11
Figure 17. Synchronous Analog Input Step Change
ANALOG INPUT
ADC OUTPUT
VALID
0ms
20ms
40ms
60ms
80ms
100ms
120ms
08
16
3-
01
2
Figure 18. Asynchronous Analog Input Step Change
allowed output data rates. The filter provides more than 53 dB
of rejection in the stop band. When the output data rate is equal
to 10 Hz, 60 Hz, or 120 Hz, the first notch occurs at a frequency
equal to the output data rate. The other notches occur at multiples
of the output data rate. Therefore, when the output data rate is
equal to 10 Hz, notches are placed at 50 Hz and 60 Hz, giving
simultaneous 50 Hz/60 Hz rejection. When the 60 Hz output
data rate is selected, 60 Hz rejection is achieved. When the
50 Hz output data rate is selected, notches are placed at 50 Hz
and multiples of 50 Hz. A notch is also placed at 60 Hz. This
gives simultaneous 50 Hz/60 Hz rejection for an output data
rate of 50 Hz.
When the output data rate is changed, DOUT/RDY goes high
and remains high until the appropriate settling time has elapsed.
Therefore, the user should complete any read operations before
changing the output data rate. Otherwise, 1s are read back from
the AD7191 as the DOUT/RDY pin is set high following the
change in output data rate.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
2030
4050
607080
90
100
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
13
Figure 19. Filter Profile for the 10 Hz Output Data Rate
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
30
60
90
120
150
180
210
240
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
14
Figure 20. Filter Profile for the 50 Hz Output Data Rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MIC2562A-1YM | IC CTRLR PCMCIA CARDBUS 14SOIC |
| MIC2027-2YWM | IC USB DISTRIB SW QUAD 16-SOIC |
| MIC2027-2YM | IC USB DISTRIB SW QUAD 16-SOIC |
| ECM12DRST | CONN EDGECARD 24POS DIP .156 SLD |
| MIC2077-1YM | IC USB DISTRIB SW QUAD 16-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7192EBZ | 功能描述:BOARD EVAL FOR AD7192 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7192EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD7192 24BIT ADC |
| EVAL-AD7193EBZ | 功能描述:EVAL BOARD FOR AD7193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7194EBZ | 功能描述:EVAL BOARD FOR AD7194 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7195EBZ | 功能描述:BOARD EVAL FOR AD7195 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。