AVCC = 4.75 V to 5.25 V," />
參數(shù)資料
型號(hào)： EVAL-AD7264EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/29頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7264
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 5 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 120mW @ 1MSPS
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7264
已供物品： 板
AD7264
Data Sheet
Rev. B | Page 6 of 28
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at T
MIN, TMAX
Parameter
2.7 V ≤ V
DRIVE ≤ 3.6 V
4.75 V ≤ V
DRIVE ≤ 5.25 V
Unit
Description
f
SCLK
200
kHz min
34
342
MHz max
AD7264
20
MHz max
AD7264-5
t
CONVERT
19 × t
SCLK
19 × t
SCLK
ns max
t
SCLK = 1/fSCLK
560
ns max
AD7264
950
ns max
AD7264-5
t
QUIET
13
ns min
Minimum time between end of serial read/bus relinquish
and next falling edge of CS
t
2
10
ns min
CS to SCLK setup time
t
3
15
ns max
Delay from 19th SCLK falling edge until D
OUTA and DOUTB are
three-state disabled
t
4
29
23
ns max
Data access time after SCLK falling edge
t
5
15
13
ns min
SCLK to data valid hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min
SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns min
SCLK low pulse width
t
8
13
ns min
CS rising edge to falling edge pulse width
t
9
13
ns max
CS rising edge to DOUTA, DOUTB high impedance/bus
relinquish
t
10
5
ns min
SCLK falling edge to D
OUTA, DOUTB high impedance
35
ns max
SCLK falling edge to D
OUTA, DOUTB high impedance
t
11
2
μs min
Minimum CAL pin high time
t
12
2
μs min
Minimum time between the CAL pin high and the CS
falling edge
t
13
3
ns min
D
IN setup time prior to SCLK falling edge
t
14
3
ns min
D
IN hold time after SCLK falling edge
t
POWER-UP
240
μs max
Internal reference, with a 1 μF decoupling capacitor
15
μs max
With an external reference, 10 μs typical
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
2 The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz.
3 The time required for the output to cross 0.4 V or 2.4 V.
CS
SCLK
1
5
19
DOUTA
THREE-STATE
t4
2
3
4
20
t5
THREE-
STATE
t7
t3
18
DB11A
DB12A
DB13A
21
31
32
33
DB1A
DB0A
DOUTB
THREE-STATE
THREE-
STATE
DB11B
DB12B
DB13B
DB1B
DB0B
06732-
002
t2
t9
t8
tQUIET
t6
Figure 2. Serial Interface Timing Diagram
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