VDD C2 R1 VIN
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EVAL-AD7366SDZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 10/29闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� BOARD EVAL FOR AD7366
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� iCMOS®
ADC 鐨勬暩(sh霉)閲忥細 2
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 1M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
杓稿叆鑼冨湇锛� ±10 V
鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛夛細 70mW @ 1MSPS
宸ヤ綔婧害锛� -40°C ~ 85°C
宸茬敤 IC / 闆朵欢锛� AD7366
宸蹭緵鐗╁搧锛� 鏉�
AD7366/AD7367
Rev. D | Page 17 of 28
D
VDD
C2
R1
VIN
VSS
C1
06703-
020
Figure 18. Equivalent Analog Input Structure
The AD7366/AD7367 can handle true bipolar input voltages.
The analog input can be set to one of three ranges: 卤10 V, 卤5 V,
or 0 V to 10 V. The logic levels on Pin RANGE0 and Pin RANGE1
determine which input range is selected as outlined in Table 8.
These range bits should not be changed during the acquisition
time prior to a conversion, but can be changed at any other time.
Table 8. Analog Input Range Selection
RANGE1
RANGE0
Range Selected
0
卤10 V
0
1
卤5 V
1
0
0 V to 10 V
1
Do not program
The AD7366/AD7367 require VDD and VSS dualsupplies for the
high voltage analog input structures. These supplies must be
equal to or greater than 卤11.5 V. See Table 7 for the require-
ments on these supplies. The AD7366/AD7367 require a low
voltage 4.75 V to 5.25 V AVCC supply to power the ADC core,
a 4.75 V to 5.25 V DVCC supply for digital power, and a 2.7 V
to 5.25 V VDRIVE supply for interface power.
Channel selection is made via the ADDR pin, as shown in
Table 9. The logic level on the ADDR pin is latched on the
rising edge of the BUSY signal for the next conversion, not
the one in progress. When power is first supplied to the
AD7366/AD7367, the default channel selection is VA1 and VB1.
Table 9. Channel Selection
ADDR
Channels Selected
0
V
A1, VB1
1
V
A2, VB2
TRANSFER FUNCTION
The output coding of the AD7366/AD7367 is twos complement.
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent
on the analog input range selected (see Table 10). The ideal
transfer characteristic is shown in Figure 19.
Table 10. LSB Sizes for Each Analog Input Range
Input
Range
AD7366
AD7367
Full-Scale
Range
LSB Size
(mV)
Full-Scale
Range
LSB Size
(mV)
卤10 V
20 V/4096
4.88
20 V/16,384
1.22
卤5 V
10 V/4096
2.44
10 V/16,384
0.61
0 V to 10 V
10 V/4096
2.44
10 V/16,384
0.61
+FSR/2 鈥� 1LSB
ANALOG INPUT
0V
ADC
CO
DE
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
鈥揊SR/2 + 1LSB
06703-
021
Figure 19. Transfer Characteristic
Track-and-Hold
The track-and-hold on the analog input of the AD7366/AD7367
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-/14-bit accuracy. The input bandwidth of
the track-and-hold is greater than the Nyquist rate of the ADC.
The AD7366/AD7367 can handle frequencies up to 35 MHz.
The track-and-hold enters its tracking mode when the BUSY
signal goes low after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 140 ns is suffi-
cient to acquire the signal to the 12-bit level for the AD7366 and
the 14-bit level for the AD7367. The acquisition time for the
卤10 V, 卤5 V, and 0 V to 10 V ranges to settle to within 卤 LSB
is typically 140 ns. The ADC returns to hold mode on the
falling edge of CNVST.
The acquisition time required is calculated using the following
formula:
tACQ = 10 脳 ((RSOURCE + R) C)
where:
C is the sampling capacitance.
R is the resistance seen by the track-and-hold amplifier looking
at the input.
RSOURCE should include any extra source impedance on the
analog input.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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