參數(shù)資料
型號(hào)： EVAL-AD7607EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR AD7607
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
在以下條件下的電源（標(biāo)準(zhǔn)）： 80mW @ 200kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7607
已供物品： 板
AD7607
Data Sheet
Rev. B | Page 20 of 32
Analog Input Antialiasing Filter
An analog antialiasing filter (a second-order Butterworth) is
also provided on the AD7607. Figure 33 and Figure 34 show
the frequency and phase response, respectively, of the analog
antialiasing filter. In the ±5 V range, the 3 dB frequency is
typically 15 kHz. In the ±10 V range, the 3 dB frequency is
typically 23 kHz.
5
0
–5
–10
–15
–20
–25
–30
–35
–40
100
1k
10k
100k
AT
T
E
NUAT
IO
N
(
d
B)
INPUT FREQUENCY (Hz)
08096-
053
±10V RANGE
±5V RANGE
AVCC, VDRIVE = 5V
fSAMPLE = 200kSPS
TA = 25°C
±10V RANGE
0.1dB
3dB
–40
10,303
24,365Hz
+25
9619
23,389Hz
+85
9326
22,607Hz
±5V RANGE
0.1dB
3dB
–40
5225
16,162Hz
+25
5225
15,478Hz
+85
4932
14,990Hz
Figure 33. Analog Antialiasing Filter Frequency Response
18
16
14
12
10
8
6
4
2
0
–2
–4
–6
10
100k
10k
1k
–8
PH
A
SE
D
EL
A
Y
(
s
)
INPUT FREQUENCY (Hz)
08096-
052
AVCC, VDRIVE = 5V
fSAMPLE = 200kSPS
TA = 25°C
±5V RANGE
±10V RANGE
Figure 34. Analog Antialiasing Filter Phase Response
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7607 let the ADC
accurately acquire an input sine wave of full-scale amplitude to
14-bit resolution. The track-and-hold amplifiers sample their
respective inputs simultaneously on the rising edge of CONVST x.
The aperture time for the track-and-hold (that is, the delay time
between the external CONVST x signal and the track-and-hold
actually going into hold) is well matched, by design, across all eight
track-and-holds on one device and from device to device. This
matching allows more than one AD7607 device to be sampled
simultaneously in a system.
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY, and it is at this point that the
track-and-holds return to track mode and the acquisition time
for the next set of conversions begins.
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 s. On the AD7607, the
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, parallel byte, or
serial interface after BUSY goes low; or, alternatively, data from
the previous conversion can be read while BUSY is high. Reading
data from the AD7607 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced
by ~1.5 dB when reading during a conversion.
ADC TRANSFER FUNCTION
The output coding of the AD7607 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/16,384. The ideal transfer characteristic is shown in Figure 35.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–FS + 1/2LSB
0V – 1LSB
+FS – 3/2LSB
ADC
CO
DE
ANALOG INPUT
+FS
MIDSCALE
–FS
LSB
±10V RANGE +10V
0V
–10V
1.22mV
±5V RANGE
+5V
0V
–5V
610V
+FS – (–FS)
214
LSB =
VIN
5V
REF
2.5V
±5V CODE =
× 8192 ×
VIN
10V
REF
2.5V
±10V CODE =
× 8182 ×
08096-
035
Figure 35. Transfer Characteristics
The LSB size is dependent on the analog input range selected.
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