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參數(shù)資料
| 型號： | EVAL-AD7634CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT AD7634 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | Q6500730 |
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Data Sheet
AD7634
Rev. B | Page 27 of 32
SLAVE SERIAL INTERFACE
The pins multiplexed on D[13:6] used for slave serial inter-
face are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK, and
RDERROR.
External Clock (MODE[1:0] = 3, EXT/INT = High)
Setting the EXT/INT = high allows the AD7634 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by CS. When CS and RD are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally
low when inactive. For detailed timing diagrams, see Figure 44
and Figure 45.
While the AD7634 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is par-
ticularly important during the last 550 ns of the conversion phase
because the AD7634 provides error correction circuitry that can
correct for an improper bit decision made during the first part
of the conversion phase. For this reason, it is recommended that
any external clock provided is a discontinuous clock that transi-
tions only when BUSY is low or, more importantly, that it does not
transition during the last 450 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 44 shows the detailed timing diagrams for this method.
After a conversion is completed, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 18 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7634 provides a daisy-
chain feature for cascading multiple converters together using the
serial data input pin, SDIN. This feature is useful for reducing
component count and wiring connections when desired, for
instance, in isolated multiconverter applications. See Figure 44
for the timing details.
An example of the concatenation of two devices is shown in
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK falling
edge when INVSCLK = low). Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot
be used because the SDIN-to-SDCLK setup time, t33, is less than
the minimum time specified. (SDCLK-to-SDOUT delay, t32, is
the same for all converters when simultaneously sampled.) For
proper operation, the SDCLK edge for latching SDIN (or
period of SDCLK) needs to be
33
32
SDCLK
t
2
/
1
Or the maximum SDCLK frequency needs to be
)
(
2
1
33
32
SDCLK
t
f
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
SDCLK
SDOUT
RDC/SDIN
AD7634
#1
(DOWNSTREAM)
AD7634
#2
(UPSTREAM)
BUSY
OUT
BUSY
DATA
OUT
SDCLK
RDC/SDIN SDOUT
SDCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
0
64
06
-04
1
Figure 43. Two AD7634 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 45 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses, and depending on the SDCLK
frequency, data can be valid on both the falling and rising edges
of the clock. The 18 bits have to be read before the current
conversion is complete; otherwise, RDERROR is pulsed high
and can be used to interrupt the host interface to prevent
incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR conver-
sion phase.
The daisy-chain feature should not be used in this mode because
digital activity occurs during the second half of the SAR conver-
sion phase likely resulting in performance degradation.
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| EVAL-AD7634EDZ | 功能描述:BOARD EVAL FOR AD7634 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7641CB | 制造商:Analog Devices 功能描述:EVAL FOR AD7641CB - Bulk |
| EVAL-AD7641CB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2 MSPS SAR ADC |
| EVAL-AD7641CBZ | 功能描述:BOARD EVALUATION FOR AD7641 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7641EDZ | 功能描述:BOARD EVAL FOR AD7641 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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