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| 型號(hào)： | EVAL-AD7660CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7660 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 200mW @ 100kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7660 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7660ASTZ-ND - IC ADC 16BIT UNIPOLAR 48-LQFP AD7660ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP AD7660ACPZRLTR-ND - IC ADC 16BIT UNIPOLAR 48LFCSP |
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REV. D
AD7660
–14–
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7660 is controlled by the signal
CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST signal operates independently of
CS and RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
For a true sampling application, the recommended operation of
the
CNVST signal is the following:
CNVST must be held HIGH from the previous falling edge
of BUSY, and during a minimum delay corresponding to the
acquisition time t8; then, when CNVST is brought LOW, a
conversion is initiated and the BUSY signal goes HIGH until
the completion of the conversion. Although
CNVST is a digital
signal, it should be designed with special care with fast, clean
edges and levels, with minimum overshoot and undershoot or
ringing. For applications where the SNR is critical, the
CNVST
signal should have a very low jitter. This may be achieved by
using a dedicated oscillator for
CNVST generation or, at least,
to clock it with a high frequency low jitter clock, as shown in
Figure 5.
t9
t8
RESET
DATABUS
BUSY
CNVST
Figure 12. RESET Timing
For other applications, conversions can be automatically initiated.
If
CNVST is held LOW when BUSY is LOW, the AD7660
controls the acquisition phase and then automatically initiates a
new conversion. By keeping
CNVST LOW, the AD7660 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up,
CNVST should be brought LOW once to initiate
the conversion process. In this mode, the AD7660 could some-
times run slightly faster than the guaranteed limit of 100 kSPS.
DIGITAL INTERFACE
The AD7660 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7660 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7660
to the host system interface digital supply. Finally, by using the
OB/
2C input pin, both twos complement or straight binary
coding can be used.
The two signals
CS and RD control the interface. CS and RD
have a similar effect because they are together internally. When
at least one of these signals is HIGH, the interface outputs are
in high impedance. Usually,
CS allows the selection of each
AD7660 in multicircuit applications and is held LOW in a
single AD7660 design.
RD is generally used to enable the con-
version result on the data bus.
t1
t3
t4
t11
CNVST
BUSY
DATA BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7660 is configured to use the parallel interface when the
SER/
PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or during
the following conversion as shown, respectively, in Figures 14 and
15. When the data is read during the conversion, however, it is
recommended that it is read-only during the first half of the
conversion phase. This avoids any potential feedthrough between
voltage transients on the digital interface and the most critical
analog conversion circuitry.
CURRENT
CONVERSION
BUSY
DATA BUS
CS
RD
t12
t13
Figure 14. Slave Parallel Data Timing for Reading
(Read after Convert)
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參數(shù)描述 |
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| EVAL-AD7660EDZ | 功能描述:BOARD EVAL FOR AD7660 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7661CB | 制造商:Analog Devices 功能描述: |
| EVAL-AD7661CBZ | 功能描述:BOARD EVALUATION FOR AD7661 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7661EDZ | 功能描述:BOARD EVAL FOR AD7661 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7662CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
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