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參數(shù)資料
| 型號： | EVAL-AD7684CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7684 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 4mW @ 5V，100kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7684 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7684BRMZ-ND - IC ADC 16BIT 100KSPS DIFF 8MSOP AD7684BRMZRL7-ND - IC ADC 16BIT 100KSPS DIFF 8MSOP |
AD7684
Rev. A | Page 5 of 16
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V, TA = 40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Throughput Rate
tCYC
100
kHz
CS Falling to DCLOCK Low
tCSD
0
μs
CS Falling to DCLOCK Rising
tSUCS
20
ns
DCLOCK Falling to Data Remains Valid
tHDO
5
16
ns
CS Rising Edge to DOUT High Impedance
tDIS
14
100
ns
DCLOCK Falling to Data Valid
tEN
16
50
ns
Acquisition Time
tACQ
400
ns
DOUT Fall Time
tF
11
25
ns
DOUT Rise Time
tR
11
25
ns
Timing Diagrams
04302-002
DOUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
Hi-Z
0
Hi-Z
tACQ
tDIS
0
14
5
tHDO
tEN
tCSD
tSUCS
tCYC
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
04302-003
500
μAI
OL
500
μAI
OH
1.4V
TO DOUT
CL
100pF
Figure 3. Load Circuit for Digital Interface Timing
0.8V
2V
0.8V
2V
tDELAY
04302-004
Figure 4. Voltage Reference Levels for Timing
04302-005
DOUT
90%
10%
tR
tF
Figure 5. DOUT Rise and Fall Timing
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。