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參數(shù)資料
| 型號(hào)： | EVAL-AD7686CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7686 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 15mW @ 500kSPS，5 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7686 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7686CCPZRL7TR-ND - IC ADC 16BIT SAR 500KSPS 10LFCSP AD7686CCPZRL-ND - IC ADC 16BIT SAR 500KSPS 10LFCSP AD7686BCPZRL7TR-ND - IC ADC 16BIT 500KSPS 10-LFCSP AD7686BCPZRL-ND - IC ADC 16BIT 500KSPS 10-LFCSP AD7686CRMZ-ND - IC ADC 16BIT 500KSPS 10MSOP AD7686BRMZ-ND - IC ADC 16BIT 500KSPS 10-MSOP AD7686CRMZRL7-ND - IC ADC 16BIT 500KSPS 10MSOP AD7686BRMZRL7-ND - IC ADC 16BIT 500KSPS 10MSOP |
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AD7686
Rev. B | Page 21 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
029
69
-04
2
CNV
SCK
SDO
SDI
AD7686
B
CNV
SCK
SDO
SDI
AD7686
A
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
303132
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1DB0DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
02
96
9-
0
43
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7686SDZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVAL BOARD 100Ksps/400Ksps 16 bit I.C RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| EVAL-AD7687CB | 制造商:Analog Devices 功能描述:EVAL BOARD 16-BIT, 250KSPS DIFFER . I.C. - Bulk |
| EVAL-AD7687CBZ | 功能描述:BOARD EVALUATION FOR AD7687 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7687SDZ | 功能描述:BOARD EVAL FOR AD7687 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7688CB | 制造商:Analog Devices 功能描述:EVAL BD FOR USE W/ EITHER THE ANLG DEVICES - Bulk |
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