參數(shù)資料
型號: EVAL-AD7722CBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/24頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7722CBZ
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 220k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: ±VREF/2
在以下條件下的電源(標準): 375mW @ 220kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7722
已供物品: 板,CD
REV. B
AD7722
–9–
PIN CONFIGURATION
44-Lead MQFP (S-44B)
3
4
5
6
7
1
2
10
11
8
9
40 39 38
41
42
43
44
36 35 34
37
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18 19 20 21 22
AD7722
DGND/DB13
DGND/DB14
DGND/DB15
SYNC
CS
DGND
CAL
AGND
REF2
AVDD
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/
DRDY
DVAL/
RD
DGND
UNI
P/
S
AGND
AGND1
CLKIN
TSI/DB3
DOE/DB4
SFMT/DB5
FSI/DB6
SCO/DB7
DV
DD
SDO/DB8
FSO/DB9
DGND/DB10
DGND/DB11
DGND/DB12
XTAL
AGND
AV
DD1
AGND
V
IN
(–)
RESET
V
IN
(+)
AGND
AV
DD
AGND
REF1
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No. Description
DVAL/
RD
5
Read input is a level sensitive logic input. The
RD logic level is sensed on the rising edge of CLKIN. This
digital input can be used in conjunction with
CS to read data from the device. The output data bus is
enabled when the rising edge of CLKIN senses a logic low level on
sensed high, the output data bits DB15–DB0 will be high impedance.
CFMT/
DRDY
4Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the
output data register.
DRDY will return high upon completion of a read operation. If a read operation does
not occur between output updates,
DRDY will pulse high for two CLKIN cycles before the next output
update.
DRDY also indicates when conversion results are available after a SYNC or RESET sequence
and when completing a self-calibration.
DGND/DB15
31
Data Output Bit (MSB).
DGND/DB14
32
Data Output Bit.
DGND/DB13
33
Data Output Bit.
DGND/DB12
34
Data Output Bit.
DGND/DB11
35
Data Output Bit.
DGND/DB10
36
Data Output Bit.
FSO/DB9
37
Data Output Bit.
SDO/DB8
38
Data Output Bit.
SCO/DB7
40
Data Output Bit.
FSI/DB6
41
Data Output Bit.
SFMT/DB5
42
Data Output Bit.
DOE/DB4
43
Data Output Bit.
TSI/DB3
44
Data Output Bit.
DGND/DB2
1
Data Output Bit.
DGND/DB1
2
Data Output Bit.
DGND/DB0
3
Data Output Bit (LSB).
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