參數(shù)資料
型號(hào)： EVAL-AD7723CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD7723
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 1.2M
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 475mW @ 1.2MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7723
已供物品： 板，CD
相關(guān)產(chǎn)品： AD7723BSZ-REEL-ND - IC ADC 16BIT SIGMA-DELTA 44MQFP
AD7723BSZ-ND - IC ADC 16BIT SIGMA-DELTA 44MQFP
AD7723
Rev. C | Page 27 of 32
SERIAL INTERFACE TO DSPs
In serial mode, the AD7723 can be directly interfaced to several
industry-standard digital signal processors. In all cases, the
AD7723 operates as the master with the DSP operating as the
slave. The AD7723 provides its own serial clock (SCO) to
transmit the digital word on the SDO pin to the DSP. The
AD7723 also generates the frame synchronization signal that
synchronizes the transfer of the 16-bit word from the AD7723
to the DSP. Depending on the serial mode used, SCO has a
frequency equal to CLKIN or equal to CLKIN/2. When SCO
equals 19.2 MHz, the AD7723 can be interfaced to the Analog
Devices ADSP-2106x SHARC DSP. With a 19.2 MHz master
clock and SCO equal to CLKIN/2, the AD7723 can be
interfaced with the ADSP-21xx family of DSPs, the DSP56002,
and the TMS320C5x-57. When the AD7723 is used in the
HALF_PWR Mode, that is, CLKIN is less than 10 MHz, then
the AD7723 can be used with DSPs, such as the
TMS320C20/TMS320C25 and the DSP56000/DSP56001.
AD7723 TO ADSP-21xx INTERFACE
Figure 47 shows the interface between the ADSP-21xx and the
AD7723. The AD7723 is operated in Mode 2 so that SCO =
CLKIN/2. For the ADSP-21xx, the bits in the serial port control
register should be set up as RFSR = 1 (a frame sync is needed
for each transfer), SLEN = 15 (16-bit word lengths), RFSW = 0
(normal framing mode for receive operations), INVRFS = 0
(active high RFS), IRFS = 0 (external RFS), and ISCLK = 0
(external serial clock).
DR
RFS
SCLK
ADSP-21xx
SDO
FSO
SCO
AD7723
01186-047
Figure 47. AD7723 to ADSP-21xx Interface
AD7723 TO SHARC INTERFACE
The interface between the AD7723 and the ADSP-2106x
SHARC DSP is the same as shown in Figure 47, but the DSP is
configured as follows: SLEN = 15 (16-bit word transfers),
SENDN = 0 (the MSB of the 16-bit word is received by the DSP
first), ICLK = 0 (an external serial clock is used), RFSR = 0 (a
frame sync is required for every word transfer), IRFS = 0 (the
receive frame sync signal is external), CKRE = 0 (the receive
data is latched into the DSP on the falling clock edge), LAFS = 0
(the DSP begins reading the 16-bit word after the DSP has
identified the frame sync signal rather than the DSP reading the
word at the same instant as the frame sync signal is identified),
and LRFS = 0 (RFS is active high). The AD7723 can be used in
Mode 1, Mode 2, or Mode 3 when interfaced to the ADSP-
2106x SHARC DSP.
AD7723 TO DSP56002 INTERFACE
Figure 48 shows the AD7723 to DSP56002 interface. To
interface the AD7723 to the DSP56002, the ADC is operated in
Mode 2 when the ADC is operated with a 19.2 MHz clock. The
DSP56002 is configured as follows: SYN = 1 (synchronous
mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous
serial clock is used), SCKD = 0 (the serial clock is external),
WL1 = l, WL0 = 0 (transfers is 16 bits wide), FSL1 = 0, and
FSL0 = 1 (the frame sync is active at the beginning of each
transfer). Alternatively, the DSP56002 can be operated in
asynchronous mode (SYN = 0).
In this mode, the serial clock for the receive section is input to
the SCO pin. This is accomplished by setting Bit SCDO to 0
(external Rx clock).
SDR
SC1
SCK
DSP56002
SDO
FSO
SCO
AD7723
01186-048
Figure 48. AD7723 to DSP56002 Interface
AD7723 TO TMS320C5x INTERFACE
Figure 49 shows the AD7723 to TMS320C5x interface. For the
TMS320C5x, FSR and CLKR are automatically configured as
inputs. The serial port is configured as follows: FO = 0 (16-bit
word transfers) and FSM = 1 (a frame sync occurs for each
transfer).
DR
FSR
CLKR
TMS320C5x
SDO
FSO
SCO
AD7723
01186-049
Figure 49. AD7723 to TMS320C5x Interface
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