AVDD = 2.7 V to " />
參數(shù)資料
型號： EVAL-AD7799EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/28頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD7799
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 470
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF/增益
在以下條件下的電源（標準）： 2.5mW @ 470SPS
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7799
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： AD7799BRU-REEL-ND - IC ADC 24BIT 3CH LP 16-TSSOP
AD7799BRUZ-REEL-ND - IC ADC 24BIT 3CH LP 16-TSSOP
AD7799BRUZ-ND - IC ADC 24BIT SIG-DEL 3CH 16TSSOP
AD7799BRU-ND - IC ADC 24BIT 3CH LP 16-TSSOP
AD7798/AD7799
Data Sheet
Rev. B | Page 6 of 28
TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter1, 2
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
Read Operation
t1
0
ns min
CS falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after CS inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to CS inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
Write Operation
t8
0
ns min
CS falling edge to SCLK active edge setup time4
t9
30
ns min
Data valid to SCLK edge setup time
t10
25
ns min
Data valid to SCLK edge hold time
t11
0
ns min
CS rising edge to SCLK edge hold time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
3
These times are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
SCLK active edge is the falling edge of SCLK.
5
These times are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured time is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, data can be reread, if required, while RDY is high, but care
should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V,
100A WITH DVDD = 3V)
ISOURCE (200A WITH DVDD = 5V,
100A WITH DVDD = 3V)
1.6V
TO
OUTPUT
PIN
50pF
04856-
002
Figure 2. Load Circuit for Timing Characterization
相關(guān)PDF資料
PDF描述
RCM15DCBH-S189 CONN EDGECARD 30POS R/A .156 SLD
EVAL-AD7785EBZ BOARD EVALUATION FOR AD7785
UVZ1J332MRD CAP ALUM 3300UF 63V 20% RADIAL
EVAL-AD7732EBZ BOARD EVAL FOR AD7732
VE-B2M-EY CONVERTER MOD DC/DC 10V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD7816/7/8EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD7816EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Single- and 4-Channel, 9 us, 10-Bit ADCs with On-Chip Temperature Sensor
EVAL-AD7817EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Single- and 4-Channel, 9 us, 10-Bit ADCs with On-Chip Temperature Sensor
EVAL-AD7818EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Single- and 4-Channel, 9 us, 10-Bit ADCs with On-Chip Temperature Sensor
EVAL-AD7839EBZ 功能描述:BOARD EVAL FOR AD7839 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*