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參數(shù)資料
| 型號： | EVAL-AD7899CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7899 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 80mW @ 400kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7899 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7899ARZ-2-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899BRZ-3-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899BRZ-1-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899ARZ-3-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899ARZ-1-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899ARSZ-3-ND - IC ADC 14BIT 400KSPS 5V 28SSOP AD7899ARSZ-2-ND - IC ADC 14BIT 400KSPS 5V 28-SSOP AD7899ARSZ-1REEL7-ND - IC ADC 14BIT 400KSPS 5V 28SSOP AD7899ARZ-1REEL-ND - IC ADC 14BIT 400KSPS 5V 28SOIC AD7899ARSZ-3REEL-ND - IC ADC 14BIT 400KSPS 5V 28SSOP 更多... |
REV. A
AD7899
–4–
TIMING CHARACTERISTICS1, 2
A, B and S
Parameter
Versions
Unit
Test Conditions/Comments
tCONV
2.2
s max
Conversion Time, Internal Clock
2.46
s max
CLKIN = 6.5 MHz
tACQ
0.3
s max
Acquisition Time
tEOC
120
ns min
EOC Pulsewidth
180
ns max
tWAKE-UP – External VREF
5
2
s max
STBY Rising Edge to CONVST Rising Edge
(See Standby Mode Operation)
t1
35
ns min
CONVST Pulsewidth
t2
70
ns min
CONVST Rising Edge to BUSY Rising Edge
Read Operation
t3
0
ns min
CS to RD Setup Time
t4
0
ns min
CS to RD Hold Time
t5
35
ns min
Read Pulsewidth
t6
3
35
ns max
Data Access Time after Falling Edge of
RD, V
DRIVE = 5 V
40
ns max
Data Access Time after Falling Edge of
RD, V
DRIVE = 3 V
t7
4
5
ns min
Bus Relinquish Time after Rising Edge of
RD
30
ns max
t8
0
ns min
BUSY Falling Edge to
RD Delay
External Clock
t9
0
ns min
CLKIN to
CONVST Rising Edge Setup Time
t10
20
ns min
CLKIN to
CONVST Rising Edge Hold Time
t11
100
ns min
CONVST Rising Edge to CLK Falling Edge
NOTES
1 Sample tested at 25
°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
DRIVE) and timed from a voltage level of V DRIVE/2.
2 See Figures 5, 6, 7, and 8.
3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5 Refer to the Standby Mode Operation section.
Specifications subject to change without notice.
(VDD = 5 V
5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN
to TMAX and valid for VDRIVE = 3 V
5% and 5 V
5% unless otherwise noted.)
1.6mA
1.6V
400 A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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