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參數(shù)資料
| 型號： | EVAL-AD7946CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7946 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 19mW @ 500kSPS，5 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7946 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7946BCPZRL7TR-ND - IC ADC 14BIT 500KSPS 10-LFCSP AD7946BCPZRL-ND - IC ADC 14BIT 500KSPS 10-LFCSP AD7946BRMZRL7-ND - IC ADC 14BIT 500KSPS 10-MSOP AD7946BRMZ-ND - IC ADC 14BIT 500KSPS SAR 10-MSOP |
AD7946
Rev. A | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on a
3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7946s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
Figure 43) SDO is driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in
the internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. For instance, with a
3 ns digital host setup time and 3 V interface, up to four AD7946s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
04656-042
CNV
SCK
SDO
SDI
AD7946
C
CNV
SCK
SDO
SDI
AD7946
A
CNV
SCK
SDO
SDI
AD7946
B
Figure 43. Chain Mode with BUSY Indicator Connection Diagram
SDOA = SDIB
DA13 DA12 DA11
SCK
12
3
31
41
42
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
413
tSCK
tSCKH
tSCKL
DA0
15
30
14
SDOB = SDIC
DB13 DB12 DB11
DA1
DB1DB0DA13 DA12
43
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC13 DC12 DC11
DA1DA0
DC1DC0DA12
17
27
28
16
29
DB1DB0DA13
DB13 DB12
tDSDOSDI
tSSCKCNV
tHSCKCNV
0
46
56
-0
43
DA0
tDSDOSDI
Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing
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