參數(shù)資料
型號： EVAL-AD7995EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/28頁
文件大小： 0K
描述： BOARD EVAL FOR AD7995
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 5.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 4.4mW @ 5.5V，3.4MHz
工作溫度： -40°C ~ 125°C
已用 IC / 零件： AD7995
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： AD7995YRJZ-1RL-ND - IC ADC 10BIT 4CH I2C SOT23-8
AD7995YRJZ-0RL-ND - IC ADC 10BIT 4CH I2C SOT23-8
AD7995YRJZ-1500RL7DKR-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7995YRJZ-0500RL7DKR-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7995YRJZ-1500RL7CT-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7995YRJZ-0500RL7CT-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7995YRJZ-1500RL7TR-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7995YRJZ-0500RL7TR-ND - IC ADC 10BIT 4CH SAR I2C SOT23-8
AD7991/AD7995/AD7999
Rev. B | Page 25 of 28
PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE
High speed mode communication commences after the master
addresses all devices connected to the bus with the master code,
00001XXX, to indicate that a high speed mode transfer is to
begin. No device connected to the bus is allowed to acknowledge
the high speed master code; therefore, the code is followed by a
NO ACK (see Figure 26). The master must then issue a repeated
start, followed by the device address and an R/W bit. The selected
device then acknowledges its address.
All devices continue to operate in high speed mode until the
master issues a stop condition. When the stop condition is
issued, the devices return to fast mode.
To guarantee performance above fSCL = 1.7 MHz, the user must
perform clock stretching—that is, the clock must be held high—for
2 μs after the ninth clock rising edge (see Figure 27). Therefore,
the clock must be held high for 2 μs after the device starts to power
0
64
61
-02
8
SDA
ACK BY
ADC
START BY
MASTER
HS MODE MASTER CODE
SERIAL BUS ADDRESS BYTE
NO ACK
19
1
9
01
0
A0
X
1
0
SCL
0
1
X
Sr
FAST MODE
HIGH SPEED MODE
Figure 26. Placing the Part into High Speed Mode
06
46
1-
03
0
SDA
11
9
D10
D9
D8
A0
1
00
0
SCL
1
D11
1
D7
D6
D5
D2
D1
D0
D4
D3
SCL (CONTINUED)
SDA (CONTINUED)
CHID1 CHID0
R/W
9
START BY
MASTER
ACK BY
ADC
NO ACK BY
MASTER
ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM ADC
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM ADC
CLOCK HIGH TIME = 2s
Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991
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