Data Sheet
AD9835
Rev. A | Page 5 of 28
TIMING CHARACTERISTICS
VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Units
Test Conditions/Comments
t1
20
ns min
MCLK period
t2
8
ns min
MCLK high duration
t3
8
ns min
MCLK low duration
t4
50
ns min
SCLK period
t5
20
ns min
SCLK high duration
t6
20
ns min
SCLK low duration
t7
15
ns min
FSYNC to SCLK falling edge setup time
t8
20
ns min
FSYNC to SCLK hold time
SCLK 5
ns max
t9
15
ns min
Data setup time
t10
5
ns min
Data hold time
t11
8
ns min
FSELECT, PSEL0, PSEL1 setup time before mclk rising edge
8
ns min
FSELECT, PSEL0, PSEL1 setup time after mclk rising edge
1 See the
section.
Pin Configuration and Function Descriptions
Timing Diagrams
MCLK
t2
t1
t3
09
63
0
-00
3
Figure 3. Master Clock
SCLK
FSYNC
SDATA
t5
t4
t6
t7
t8
t10
t9
D14
D15
D0
D1
D2
D15
D14
09
630
-00
4
Figure 4. Serial Timing
t11A
t11
VALID DATA
MCLK
FSELECT
PSEL0, PSEL1
09
63
0-
0
05
Figure 5. Control Timing