參數(shù)資料
型號(hào)： EVAL-ADCMP561BRQZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION ADCMP561BRQZ
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，比較器
已用 IC / 零件： ADCMP561
已供物品： 板
相關(guān)產(chǎn)品： ADCMP561BRQZ-ND - IC COMPARATOR PECL DUAL 16QSOP
ADCMP561BRQ-ND - IC COMP PECL DUAL HS 16-QSOP
ADCMP561/ADCMP562
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04687-0-002
ADCMP561
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
VDD
VEE
LEA
–INB
+INB
QB
GND
VCC
LEB
04687-0-003
ADCMP562
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
VDD
VEE
LEA
VDD
+INA
HYSA
–INB
QB
GND
VCC
LEB
VDD
+INB
HYSB
Figure 4. ADCMP561 16-Lead QSOP Pin Configuration
Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP561
ADCMP562
Mnemonic
Function
1
VDD
Logic Supply Terminal.
1
2
QA
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
2
3
QA
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
3
4
VDD
Logic Supply Terminal.
4
5
LEA
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In the latch mode (logic low), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5
6
LEA
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
6
7
VEE
Negative Supply Terminal.
7
8
INA
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
8
9
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting
A input must be driven in conjunction with the inverting A input.
10
HYSA
Programmable Hysteresis Input.
11
HYSB
Programmable Hysteresis Input.
9
12
+INB
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting
B input must be driven in conjunction with the inverting B input.
10
13
INB
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
11
14
VCC
Positive Supply Terminal.
12
15
LEB
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to placing the comparator in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
13
16
LEB
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to placing the comparator in the latch mode. LEB must be
driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.
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