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| 型號(hào)： | EVAL-ADCMP565BPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION ADCMP565BPZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，比較器 |
| 已用 IC / 零件： | ADCMP565 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADCMP565BPZ-ND - IC COMP DUAL ULTRA-FAST 20-PLCC ADCMP565BP-ND - IC COMP DUAL ULTRA-FAST 20-PLCC |
ADCMP565
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
3
2
1
20
19
910
11
12 13
18
17
16
15
14
4
5
6
7
8
PIN 1
IDENTIFIER
NC = NO CONNECT
GND
LEA
NC
VEE
GND
LEB
NC
VCC
ADCMP565
TOP VIEW
(Not to Scale)
QA
NC
QB
–IN
A
+I
NA
NC
+I
NB
–IN
B
QA
LEA
LEB
QB
02820-0-002
Figure 2. ADCMP565 Pin Configuration
Table 3. ADCMP565 Pin Descriptions
Pin No.
Mnemonic
Function
1
NC
No Connect. Leave pin unconnected.
2
QA
One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.
3
QA
One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.
4
GND
Analog Ground
5
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
6
NC
No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
7
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
8
VEE
Negative Supply Terminal
9
INA
Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.
10
+INA
Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
be driven in conjunction with the inverting A input.
11
NC
No Connect. Leave pin unconnected.
12
+INB
Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
be driven in conjunction with the inverting B input.
13
INB
Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
in conjunction with the noninverting B input.
14
VCC
Positive Supply Terminal
15
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
16
NC
No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
17
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
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